Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MULTI-LINK ERROR CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS54100604
Kind Code:
A
Abstract:

PURPOSE: To improve transmission efficiency by making preceding node information ineffective in case of occurrence of a transmission error and then by adding a new check code.

CONSTITUTION: A data block transmitted from preceding node A is inputted from selector circuit SEL(1) to check CHK and result R is fed back to SEL(1), thereby using the circuit as generator GEN this time. Data from the preceding node, on the other hand, are stored temporarily in buffer memory BFM and then sent out from selector circuit SEL(2) with the check result added. Without being inputted to check circuit CHK, data until the node two stages ahead are transmitted by timing control circuit CTLTIM directly from the gata circuit to next node B.


Inventors:
KOJIMA TAKUTO
NAITOU SHIYUNICHI
Application Number:
JP709378A
Publication Date:
August 08, 1979
Filing Date:
January 25, 1978
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
FUJITSU LTD
International Classes:
H04L1/00; H04Q11/04; (IPC1-7): H04L1/10; H04L11/16; H04L11/20



 
Previous Patent: JPS54100603

Next Patent: SUBSCRIBER LINE CONCENTRATION SYSTEM