PURPOSE: To perform the communication of data between a processor having the master right and 2 or more slave processors with addition of a small quantity of hardware by mapping a memory of a certain slave processor selected by a master processor into a fixed area of a system memory space as a shared memory.
CONSTITUTION: In seems that both a local memory 12 and a shared memory 13 are mapped by a CPU 11 of a processor unit 17. Then another processor unit has the master right and has an access to the memory 13 via an external system bus 18. In this case, the unit 17 checks a shared memory ownership flag 19 and writes the acquisition of the ownership into the flag 19 as long as any processor has no ownership. Thus the master right is owned by the unit 17. Then the serial number of the unit 17 having the memory 13 to receive an access is written into a processor selector register contained in a processor selector 14.
JP2752487 | [Title of Invention] Network Interface |
WO/2003/088070 | PROJECTOR DEVICE NETWORK MANAGEMENT SYSTEM |
JPS58176728 | DISPLAY SYSTEM OF CONNECTING STATE |