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Title:
MULTI-OUTPUT DETERMINATION CIRCUIT
Document Type and Number:
Japanese Patent JP2009303321
Kind Code:
A
Abstract:

To provide a multi-output determination circuit which can reduce its cost by reducing the number of comparators.

This multi-output determination circuit, which determines whether or not one input voltage of a plurality of input voltages is at an upper limit voltage value or higher, is equipped with: the first diode OR, which consists of a plurality of first diodes, where a plurality of input voltages are connected severally to their anodes and whose cathodes are connected in common; an upper limit reference voltage generating means, which has the first resistor, the first diode; and the second resistor connected in series between the first and second power potentials and which generates an upper reference voltage, based on the cathode of the first diode, and the first comparator which compares the voltage of the cathode of the first diode OR with the upper limit reference voltage.


Inventors:
TAKEBAYASHI KENICHI
SUZUKI KOJI
SENOO KAZUTAKA
Application Number:
JP2008152666A
Publication Date:
December 24, 2009
Filing Date:
June 11, 2008
Export Citation:
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Assignee:
KEIHIN CORP
International Classes:
H02P23/00; H02P21/22; H02P27/08
Domestic Patent References:
JPS52144247A1977-12-01
JPH09119949A1997-05-06
JPS5380340U1978-07-04
JPS5863569U1983-04-28
JPH07297647A1995-11-10
JPS531567A1978-01-09
JPH05333319A1993-12-17
JPS52144247A1977-12-01
JPH09119949A1997-05-06
Attorney, Agent or Firm:
Akira Matsumoto
Kenji Ito