To provide a multi-phase clock generation circuit for lowering the frequency of a reference clock without using many delay elements, reducing a mounting area by a simple circuit and being provided at a low cost.

This circuit is provided with a reference clock generation circuit 101 for generating the reference clock equal to the frequency (fo) of the multi- phase clock of n phases, a doubling circuit 102 for doubling the reference clock and generating a double clock, an n/4 phase clock generation circuit 103 for preparing an n/4 phase clock from the double clock, inverters 107 and 108 for inverting the n/4 phase clock and a 2 frequency divider circuit 104 for frequency dividing the n/4 phase clock into two and outputting it to a shift register. By clocking the shift register by the first phase clock of the n/4 phase clock, a second phase clock for which it is delayed for T/n and the n/4 phase clock inverted in the inverter, the multi-phase clock is generated.