Title:
多相クロック生成回路
Document Type and Number:
Japanese Patent JP4063001
Kind Code:
B2
Abstract:
A multi-phase clock generation circuit includes a clock generation circuit, first frequency divider circuit, first clock selection circuit, second to nth frequency divider circuits, second to nth clock selection circuits, and clock selection control section. The clock generation circuit generates 2 n (n is a positive integer) reference clock signals having the same frequency and different phases. The frequency divider circuit frequency-divides one of the reference clock signals by 2 to generate clock signals 180° out of phase with each other. The first clock selection circuit selects one of each of the clock signals and a corresponding reference clock signal and outputs the selected signals as clock pulses. Each of the second to nth frequency divider circuits frequency-divides a clock pulse to generate clock signals 180° out of phase with each other. Each of the second to nth clock selection circuits selects one of each of the clock signals and a corresponding one of the reference clock signals to output the selected signals as clock pulses. The clock selection control section controls the first to nth clock selection circuits in accordance with a set frequency division ratio.
Inventors:
Tsutomu Sasaki
Application Number:
JP2002211637A
Publication Date:
March 19, 2008
Filing Date:
July 19, 2002
Export Citation:
Assignee:
NEC
International Classes:
G06F1/06; H03K5/15; H03K23/00
Domestic Patent References:
| JP2001350539A | ||||
| JP2001381731A | ||||
| JP9232947A |
Other References:
Lixin Yang; Yijun Zhou; Jiren Yuan,A non-feedback multiphase clock generator,Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium,米国,2002年 5月29日,Volume 4,Page(s):IV-389 - IV-392
Attorney, Agent or Firm:
Umeo Yamauchi