Title:
直列入/出力インターフェースを有するマルチポートメモリ素子
Document Type and Number:
Japanese Patent JP4711646
Kind Code:
B2
Abstract:
The multi-port memory device includes a plurality of ports supporting serial I/O interface, and the plurality of ports includes a transmission pad and a reception pad. The multi-port memory device includes: a memory core; a control block for generating an internal command signal, an internal address and a control signal, which correspond to the command and are necessary for an operation of the memory core, using commands and addresses inputted to the plurality of ports packet form; and a mode selection block for combining signals applied to plurality of mode selection pads and generating a test mode flag signal, in which I/O data assigned to the transmission pad and the reception pad in a test mode in response to the test mode flag signal are exchanged with the memory core through the ports.
Inventors:
Lee Australia
Application Number:
JP2004195067A
Publication Date:
June 29, 2011
Filing Date:
June 30, 2004
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
G01R31/28; G11C5/02; G11C29/04; G11C7/10; G11C8/16; G11C11/401; G11C11/4063; G11C29/00; G11C29/26
Domestic Patent References:
| JP2002108695A | ||||
| JP3003189A |
Attorney, Agent or Firm:
Teruichi Hase
Maki Kamiya
Maki Kamiya