Title:
MULTI-PORT RAM MEMORY CELL
Document Type and Number:
Japanese Patent JP3153568
Kind Code:
B2
Abstract:
PURPOSE: To attain a reading operation at a high speed and synchronously with a clock signal by forming a transistor train between a bit line and a power supply of a low potential and performing the conduction control with a prescribed clock signal.
CONSTITUTION: A memory cell 11 is provided with an address decoder 14 which receives the address signal from an input/output circuit 3 and selects and designates a word line corresponding to a decoding operation. Such cells 11 are arranged in a matrix form as the memory cells of a 3-port RAM. An F/F circuit 12 contains an FFT which undergoes the conduction control with the stored data and an FFT which designates the read data when the stored data are read out. If a clock signal CLK is set at a high level under such conditions, a bit line is set in an ABL state with a precharging transistor of the circuit 3 and an NFETA12 of the cell 11 conducts. In this case, however, the NFETB11- B13 never conduct since the signal CLK is inverted and set at the potentials of the bit lines of the NFET B11-B13. Thus a high speed reading operation is attained synchronously with the signal CLK.
Inventors:
Usami, Masayoshi
Muroya, Yukinori
Muroya, Yukinori
Application Number:
JP16287191A
Publication Date:
April 09, 2001
Filing Date:
July 03, 1991
Export Citation:
Assignee:
TOSHIBA CORP
TOSHIBA MICRO ELECTRON KK
TOSHIBA JOHO SYST KK
TOSHIBA MICRO ELECTRON KK
TOSHIBA JOHO SYST KK
International Classes:
G11C8/16; G11C11/41; (IPC1-7): G11C11/41
Attorney, Agent or Firm:
三好 秀和 （外４名）