To provide a multi-processor system for reducing the latency of a memory access as a whole system.

Installed, between a processor 8 and a main memory 9, is a memory management mechanism 10 comprising: access data moving means for, by using an access performed by a certain processor 8 to the main memory 9 of another node as a trigger, acquiring data accessed by the processor 8 from the main memory 9, and for moving the data to the main memory 9 paired with the processor 8 which has performed the access; storage capacity securing means for securing a capacity for storing the access data by abandoning a portion of data from the main memory 9 for storing the access data; storage memory selection means for selecting the main memory 9 for storing the abandoned data instead from among the plurality of main memories 9; and abandoned data storage means for storing the abandoned data in the selected main memory.