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Title:
MULTI-PROCESSOR SYSTEM
Document Type and Number:
Japanese Patent JPS5897751
Kind Code:
A
Abstract:

PURPOSE: To realize a backup which does not cause a breakdown of system as a whole with high reliability and high efficiency, by using together a double ratio synchronous operation system, a queuing spare operation system and an N+1 substitute system in accordance with the function of each processor.

CONSTITUTION: A processor CPA which works with a dual system is used as a master processor, and a processor CP'A works as a slave processor. These two processors perform the synchronous collation of data through a synchronous data transmission/reception line 3 and at the same time work together with a mutual check through a mutual monitor line 2. The processors CPB and CP'B apply a queuing spare system and connected to each other via a mutual monitor line 4. The processor CPB has an on-line operation as the using side; while the processor CP'B is always ready for an operation as the queuing side respectively


Inventors:
UEDA KENICHI
SUGANO ATSUSHI
HONDA KUNIO
Application Number:
JP19592581A
Publication Date:
June 10, 1983
Filing Date:
December 04, 1981
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F11/20; G06F15/16; G08B29/16; (IPC1-7): G06F15/16
Domestic Patent References:
JPS4928211A1974-03-13
JPS4871157A1973-09-26
JPS4934748A1974-03-30
Attorney, Agent or Firm:
Toshio Nakao