Title:
MULTI-PROCESSOR SYSTEM
Document Type and Number:
Japanese Patent JPS6332649
Kind Code:
A
Abstract:
PURPOSE:To decrease the access frequency to a common bus by connecting a common memory and a bus arbiter to a common bus, delivering a permission signal from the bus arbiter to give a reading request to the common memory and holding this request data. CONSTITUTION:When the program reading requests are produced from processor units PU0-n, an access request is sent to a bus arbiter ABT1 via a program reading common bus CBUS1. The arbiter ABT1 controls the access requests given from the units PU0-n and allocates the use of the CBUS1 to these units PU0-n respectively. When the arbiter ABT1 gives permission, the permission signals are given to the units PU0-n. Detecting those permission signals, the units PU0-n transmit the reading request signals and the address information. The data read out of a common memory CM1 are received and transmission of the access requests, reading request and the address information are stopped. Then a program reading action is through.
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Inventors:
OKI FUMIO
Application Number:
JP17705586A
Publication Date:
February 12, 1988
Filing Date:
July 28, 1986
Export Citation:
Assignee:
NEC CORP
International Classes:
G06F15/16; G06F12/00; G06F13/36; G06F15/177; (IPC1-7): G06F15/16
Attorney, Agent or Firm:
Murao Mikio