Title:
多段アレイキャパシター及びその製造方法
Document Type and Number:
Japanese Patent JP3995596
Kind Code:
B2
Abstract:
A capacitor includes multiple tiers (302, 304, 306, 1210, 1212, 1310, 1312, 1380, FIGS. 3, 12, 13), which provide capacitance to a load at different inductance values. Each tier includes multiple layers (311-325, 1220, 1222, 1320, 1322, 1382, FIGS. 3, 12, 13) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias (330, 332, 334, 1230, 1232, FIGS. 3, 12) that extend through some or all of the tiers. In another embodiment, one or more tiers (1310, 1312, FIG. 13) are located in a center region (1404, FIG. 14) of the capacitor, and one or more other tiers (1380, FIG. 13) are located in a peripheral region (1408, FIG. 14) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers (1370, FIG. 13) of patterned conductive material. The capacitors of the various embodiments can be used as discrete devices, which are mountable on or embeddable within a housing (e.g., a package, interposer, socket or PC board), or they can be integrally fabricated within the housing.
Inventors:
Mosley, Rally, Yi
De, hong
Figueroa, david, jei
Brown, kenneth, em
Chakra Beauty, Kishore, Kay
Rodriguez, Jorge, Py
De, hong
Figueroa, david, jei
Brown, kenneth, em
Chakra Beauty, Kishore, Kay
Rodriguez, Jorge, Py
Application Number:
JP2002555429A
Publication Date:
October 24, 2007
Filing Date:
November 28, 2001
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
H01G2/06; H01G4/30; H01G4/38; H05K1/00; H05K1/16
Domestic Patent References:
| JP5166668A | ||||
| JP11204372A | ||||
| JP7142283A | ||||
| JP57211219A | ||||
| JP4172702A | ||||
| JP6302966A | ||||
| JP4065107A |
Attorney, Agent or Firm:
Koichiro Kato