PURPOSE: To realize a multi-stage counter circuit with simple constitution by applying count of a prescribed digit, using a count means to count low-order digits and using a sequential means to count high-order digits and applying carryout decision to the result of count via a time division processing means.

CONSTITUTION: In counting plural digits by a multi-stage counter circuit 2a, the low-order digits at a fast speed are counted by a counter means 10 comprising series connection of N-adic counters and high-order digits are counted by a sequential means 20, the result is subject to time division processing by a time division processing means 30 and carry-out decision is applied to the result of processing. Thus, the number of N-adic counters connected in series is reduced remarkably to reduce component cost and the multi-stage counter circuit smaller than the mount space is formed.