PURPOSE: To reduce the maximum value of the operation confirming time of a multistage counter by providing a negative logic AND gate (or positive logic OR gate) and arranging the leading timing of a signal for shifting a 2nd and succeeding digit.

CONSTITUTION: Digit shift signals CM-N, BM-N for a binary hexadecimal counter (CNTM) 1M of the M-th stage are given to negative logic AND gates 41, 42 together with computing signals UP-N, DN-N and digit shift signals LCM-N, LBM-N being the outputs are given to computing signal input terminals UP, DN of the CNT(M+1). The timing when the carry signals LC1-N∼LCN-N rise is according to an addition signal UP-N by each negative logic AND gate 41. Thus, even when number of stages N is increased, only the delay time according to the number of the negative logic AND gates 41 is caused and the maximum value of the operation confirming time of the entire multi-stage counter is decreased. This is applied also to the down-counting.