PURPOSE: To obtain a frequency division signal whose jitter is reduced by branching and fetching an input signal inputted to a 1st stage of a frequency divider means as a timing pulse and outputting a frequency division signal outputted from a final stage of the frequency divider means through retiming.
CONSTITUTION: In a 1/64 frequency division signal (2) outputted from a last stage 1/2 frequency divider 41, a high level and a low level are replaced at an up edge for each of 32 pulses of a frequency divider input signal (1) inputted to a 1st stage 1/2 frequency divider 41 and the result is a fluctuated 1/64 frequency division signal (3) due to jitter. When a D flip-flop 11 is operated at a down edge, the Q output of the D flip-flop 11 keeps the state of a D input at the moment when the frequency divider input signal (1) being the input of a clock input terminal C falls down from a high level to a low level till a down edge of the succeeding frequency divider input signal (1). Then the Q output of the D flip-flop 11 is a 1/64 frequency division signal (4). Then the 1/64 frequency division signal (3) fluctuated due to jitter is subjected to retiming, jitter of the 1/2 frequency divider 41 is suppressed to obtain the 1/64 frequency division signal (4).
HIROTA TETSUO
OHIRA TAKASHI
