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Title:
MULTI-STAGE NUMERIC COUNTER OSCILLATOR
Document Type and Number:
Japanese Patent JP2005198296
Kind Code:
A
Abstract:

To provide a numeric counter oscillator (NCO) of high-level accuracy for making a frequency resolution more flexible.

An NCO has a quotient accumulator and a remainder accumulator. The quotient accumulator has a programmable input for receiving a quotient value, a reference clock input and a multi-bit output. The multi-bit output is adapted to be increment in response to each reference clock term. The remainder accumulator comprises programmable inputs for receiving respective remainder and divisor values, a reference clock input and a multi-bit output representing an accumulated digital remainder sum less than a predefined digital integer. The remainder accumulator further comprises a comparator having a first input for receiving a programmed divisor value, and a second input for receiving the remainder accumulator multi-bit output.


Inventors:
REICHERT PETER
Application Number:
JP2004379846A
Publication Date:
July 21, 2005
Filing Date:
December 28, 2004
Export Citation:
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Assignee:
TERADYNE INC
International Classes:
G06F1/03; H03K23/66; G01R31/3183; (IPC1-7): H03K23/66; G01R31/3183
Domestic Patent References:
JPS62225027A1987-10-03
JPH01151316A1989-06-14
JPH0199322A1989-04-18
JPH0296429A1990-04-09
JP2002182898A2002-06-28
JPH0983352A1997-03-28
Attorney, Agent or Firm:
Kazuo Shamoto
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Otsuka Naruhiko



 
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