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Title:
MULTI-TASK CONTROLLING DEVICE
Document Type and Number:
Japanese Patent JPS60118939
Kind Code:
A
Abstract:

PURPOSE: To relieve the load of software of a master CPU side by using an element being a parallel data input/output element and also being a mutli-task controller.

CONSTITUTION: Ports 1 (P1D), 2 (P2D) are provided, and when the input/output direction of the ports is written from a master CPU to a command parameter register CPIO, and a command PMOD14 is written in a command state register CNST, the device sets the input/output direction of the port 1 (P1D) and 2 (P2D). Moreover, the device generates interruption to a master CPU according to a command from the task during execution, and has a function controlling the execution of task, and stops the task by the interrupting processing by the input to a port 3 (P3D) or starts an external event.


Inventors:
NAKADE TOSHIMITSU
KUKI MASARU
HAYASHI HIROTAKE
UNO TAKAAKI
Application Number:
JP22812383A
Publication Date:
June 26, 1985
Filing Date:
November 30, 1983
Export Citation:
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Assignee:
SHARP KK
International Classes:
G06F9/46; G06F15/16; G06F15/177; (IPC1-7): G06F9/46
Domestic Patent References:
JPS5716950U1982-01-28
JPS57131580U1982-08-16
Attorney, Agent or Firm:
Sugiyama Takeshi



 
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