多値記憶回路およびその駆動方法

Japanese Patent JP4339807

B2

To separate an input and an output of a multi-level storage circuit from each other with fewer number of elements than heretofore.

The drain electrode D of a mono-electron transistor is connected to a source electrode of a field effect transistor 2, the drain electrode of the field effect transistor 2 is connected to one end of a load element, the other end of the load element 3 is connected to a power source terminal 5, and a source electrode S of the mom-electron transistor 1 is connected to a ground terminal 6. Also, a first electrode G of the mono-electron transistor 1 is connected to a connection point of the field effect transistor 2 and the load element 3, further his connection point is connected to the output terminal. Also, a second gate electrode Ginis newly provided at the mono-electron transistor 1, and this second gate electrode Ginis connected to an input terminal 7. Furthermore, an accumulation capacitor 8 is connected between an output terminal 8 and the ground terminal 6. a unipolar or a bipolar voltage pulse, in which the rise time and the fall time are different, is given to the input terminal 7 and the data value stored in the multi-level storing circuit, is rewritten.

COPYRIGHT: (C)2007,JPO&INPIT

Hiroshi Inokawa
Katsuhiko Nishiguchi

JP2005092433A

October 07, 2009

March 28, 2005

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Nippon Telegraph and Telephone Corporation

G11C11/21; G11C11/56; H01L27/10; H01L29/66

JP2002289833A
JP2004281465A

Masaki Yamakawa
Hiroro Kurokawa
Shigeki Yamakawa

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