To improve image quality by regulating the deviation of the writing positions of plural light beams in a main scanning direction with high accuracy.

A PLL circuit is composed of a phase comparator 305, an LPF (low-pass filter) 309 and a VCO(voltage control oscillator) 303b. A CPU 301 has a D/A converter 301a for converting a digital value (for example, 8 bit) to an analog value, etc., therein and changes the phase difference of the pixel clock signals CLK 1 and CLK 2 outputted from VCOs 303a and 303b by changing the value of the data to be set in the D/A converter 301a at the time of writing position regulation. The data on the reference control voltage indicating the phase difference between the pixel clock signals CLK 1 and CLK 2 when the writing positions of laser beams LB 1 and LB 2 coincide is stored in a non-volatile memory 310. A CPU 301 sets the data on the reference control voltage in the D/A converter 301a and outputs the control voltage Vcont from the D/A converter 301a to the VCO 303a at the time of image formation.