To reduce circuit scale by sharing a serial/parallel(S/P) converting circuit for the parallel conversion of serial input data and the serial conversion of parallel correction data.

A full adder logic circuit 1 is composed of an adder circuit 13 and an FF 16 for carry-up. Serial input data 4 are passed through the adder circuit 13 and inputted to an S/P converting circuit 3 as the arithmetic result 5. In this case, a shift register 31 consists of a FIFO and while a correction value/arithmetic result switching control signal 8 is '0', correction data HD0-HDn are parallelly loaded from a correction data memory 2 but when the signal 8 becomes '1', these data are sent to the full adder logic circuit 1 as serial correction data 10 by a transfer clock 7. The added/corrected arithmetic result 5 is successively inputted from the most significant digit of shift register 31 as serial corrected data, are successively shifted and appear at terminals Q0-Qn as parallel corrected data 6.