Title:
MULTICHIP MODULE AND ITS MANUFACTURE
Document Type and Number:
Japanese Patent JP3210503
Kind Code:
B2
Abstract:
PURPOSE: To obtain a multichip module capable of always holding and realizing stable functions by arranging input/output terminal pins-mounting pads in a row and by staggering leading portions for inner layer wiring for each pad.
CONSTITUTION: An input/output terminal pin 4 as a multichip module electrically connected to a chip type electronic part 2 joined by mount bonding to the surface of a predetermined region of a second signal wiring layer 1b is electrically connected through an input/output terminal pin mounting pad 4a located at a socalled viahole leading portion on the surface of a first signal wiring layer 1a via a second signal wiring layer 1b and a first signal wiring layer 1a. Here, the input/output terminal pin mounting pads 4a are arranged in a row, and the leading portions 4b of the inner layer wiring led out through the first signal wiring layer 1a for the input/output terminal pins mounting pads 4a are staggered in the arrangement.
Inventors:
Yoshitaka Fukuoka
Application Number:
JP24530493A
Publication Date:
September 17, 2001
Filing Date:
September 30, 1993
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L25/18; H01L23/057; H01L23/10; H01L23/538; H01L25/04; (IPC1-7): H01L25/04; H01L25/18
Domestic Patent References:
| JP5243481A | ||||
| JP58169950A | ||||
| JP297042A | ||||
| JP5980957A |
Attorney, Agent or Firm:
Saichi Suyama
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