PURPOSE: To increase the operating speed and to miniaturize the circuit scale and size of such a multiinput arithmetic circuit that processes the added results of multiinput adding circuits with a logic circuit.

CONSTITUTION: This multiinput arithmetic circuit is provided with plural multiinput adding circuits 1A-1D, a simple logic circuit 10 which produces plural processed results by performing prescribed operation on the added results of the circuits 1A-1D, and multiinput adding circuits 17 and 7 which add the plural processed results to each other. Then the added results of the circuits 1A-ID in the prestage are supplied to the circuit 10 in a redundant expression composed of summed outputs and carried outputs and the circuit 10 supplies the plural processed results to the circuits 17 and 7 in its post stage in a redundant expression. The circuits 17 and 7 output the added results in an ordinary binary expression.