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Title:
MULTILAYER CAPACITOR, ITS MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE COMPRISING IT, ELECTRONIC CIRCUIT BOARD
Document Type and Number:
Japanese Patent JP2002260959
Kind Code:
A
Abstract:

To provide a multilayer capacitor having a high capacitance per unit mounting area as a decoupling capacitor being disposed on the periphery of an LSI operating at high speed and compensating for voltage drop when the load on the LSI is varied.

In the multilayer capacitor where dielectric and inner electrode are laid alternately in layers in order to reduce self inductance, a plurality of terminal electrodes for external connection are provided, respectively, on two bottom faces while being arranged two-dimensionally. The inner electrode is provided alternately with a layer connected electrically with the power supply of the LSI and a layer being connected electrically with the ground of the LSI and arranged with terminal electrodes connected, through via electrodes, with the inner electrodes connected electrically with the power supply of the LSI and terminal electrodes connected, through via electrodes, with the inner electrodes connected electrically with the ground of the LSI.


Inventors:
MORI TORU
YAMAZAKI TAKAO
NAKASE KOICHIRO
Application Number:
JP2001056950A
Publication Date:
September 13, 2002
Filing Date:
March 01, 2001
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01G4/30; H01G4/38; H01L23/498; H01L23/64; H01G4/12; H05K1/14; H05K1/16; H05K1/18; H05K1/02; H05K1/03; H05K3/40; (IPC1-7): H01G4/38; H01G4/12; H01G4/30; H05K1/14; H05K1/18
Attorney, Agent or Firm:
Nobuo Takahashi (3 outside)