To manufacture a multilayer capacitor at a high yield, and to suppress its warpage.
This multilayer capacitor is composed by sticking two or more laminated bodies 20A, 20B each including resin layers and metal layers alternately laminated multiple times in the thickness direction, and having warpage, in each of which the front and back surfaces are covered with a surface layer containing a resin material, one of the front and back surfaces is composed of a first surface 30 being a smooth surface without having a recessed part, and the other surface thereof is composed of a second surface 32 having recessed parts 34. In the multilayer capacitor, at least any two of the adjacent laminated bodies 20A, 20B are pasted to each other through the mutual first surfaces 30 or the mutual second surfaces 32. This method of manufacturing the same, and this circuit board and this electronic device using the same are also provided.
ITO CHIHARU
KAKO TOMONAO
| JP2003264119A | 2003-09-19 | |||
| JP2006245175A | 2006-09-14 |