Title:
集積回路向け多層共配置
Document Type and Number:
Japanese Patent JP7299234
Kind Code:
B2
Abstract:
Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs. The method includes iteratively adjusting a location of the standard cells with or without a location of inter-tier connections so as to converge the location of the standard cells with or without the location of the inter-tier connections to optimized locations or legal locations.
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Inventors:
Shoe, Xiao Ching
Klein, Brian Tracy
Moore, Stephen Lewis
Singha, Saurab Pijuskumar
Klein, Brian Tracy
Moore, Stephen Lewis
Singha, Saurab Pijuskumar
Application Number:
JP2020552356A
Publication Date:
June 27, 2023
Filing Date:
March 19, 2019
Export Citation:
Assignee:
Arm limited
International Classes:
H01L21/82; G06F30/392; G06F30/394; H01L27/00
Domestic Patent References:
| JP2008243993A | ||||
| JP9289253A |
Foreign References:
| US20150118793 | ||||
| US20100095263 |
Other References:
C. Ababei et al.,Placement and Routing in 3D Integrated Circuits,IEEE Design & Test of Computers,米国,IEEE,2005年11月,Vol.22 No. 6,520-531
Attorney, Agent or Firm:
Makoto Onda
Hironobu Onda
Atsushi Honda
Hironobu Onda
Atsushi Honda