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Title:
MULTILAYER INTERCONNECTION CIRCUIT BOARD AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPS649694
Kind Code:
A
Abstract:

PURPOSE: To make it possible to form circuits of a high density and high reliability by forming the circuit of the outermost layer by a plating method in a multilayer interconnection circuit board in which circuits of two or more layers are formed on one surface of the base material.

CONSTITUTION: After lower circuits 2 are formed on the surface of a base material 1 by a plating method, circuit connecting sections 4 are formed on the lower circuits 2 and an insulating material layer 5 is formed so as to cover the lower circuits 2 and the circuit connecting sections 4. Then, after removing the surface layer of the insulating material layer 5 to expose the circuit connecting sections 4, upper circuits 3 are formed on the surface of the insulating material layer 5 by plating. The circuits 3 are formed by plating copper or the like, and it is preferred to employ a semi-additive method. Thus, in forming the upper circuits 3, the formation of the circuits 3 can be performed on the surface of the insulating material layer 5 which has become a planar surface. For this, micro patterns can be formed easily and very precisely.


Inventors:
YAMAKAWA YOSHINAGA
TAKAHASHI NOBUYUKI
SUZUKI TOSHIYUKI
Application Number:
JP16559987A
Publication Date:
January 12, 1989
Filing Date:
July 01, 1987
Export Citation:
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Assignee:
TOYO GIKEN KOGYO KK
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
H05K3/46; (IPC1-7): H05K3/46
Domestic Patent References:
JPS61127196A1986-06-14
JPS55158697A1980-12-10
JPS4894866A1973-12-06
JPS5662398A1981-05-28
JPS52145773A1977-12-05
JPS5762593A1982-04-15
Attorney, Agent or Firm:
Ishida Choshichi



 
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