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Patent Searching and Data


Title:
MULTILAYER PRINTED WIRING BOARD
Document Type and Number:
Japanese Patent JPH04148593
Kind Code:
A
Abstract:

PURPOSE: To check whether or not the wiring pattern is passing the wiring inhibited region at the stage of an inner layer or whether or not it comes too close to the wiring inhibited region by putting a line, which shows the contour of the wiring inhibited region to a mechanical hole, into it as a pattern.

CONSTITUTION: The contour pattern 1 surrounds the outside of the wiring inhibited region 3 in and around a mechanical hole 2. For a normal wiring pattern 4 is passing avoiding the mechanical hole, and there is no fear of short circuit or wire breaking about this wiring pattern 4. A wiring pattern 6 is passing above the mechanical hole 2, so this is an abnormal pattern. In case that this wiring patterns 6 occurs by any cause, the abnormality is detected by the shape of the short with the contour pattern 1. This abnormality can be detected by optical inspection or by the check of an original picture or an inner layer. Moreover, by connecting the contour pattern 1, which shows the inhibition area to a hole, etc., and putting out the check point, it can be electrically shorted and detected.


Inventors:
YOSHIDA HARUMI
OMAE KENICHI
Application Number:
JP27366390A
Publication Date:
May 21, 1992
Filing Date:
October 12, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
H05K1/02; H05K3/00; H05K3/46; (IPC1-7): H05K1/02; H05K3/00; H05K3/46
Attorney, Agent or Firm:
Uchihara Shin