Title:
MULTILAYER STRUCTURE, ELECTRONIC EQUIPMENT AND METHOD FOR MANUFACTURING MULTILAYER STRUCTURE
Document Type and Number:
Japanese Patent JP2012037406
Kind Code:
A
Abstract:
To reduce warpage of a substrate caused by stress induced in a multilayer structure.
The multilayer structure comprises a substrate 20, a multilayer wiring structure (30, 40, 50) formed on a first principal surface of the substrate, a cavity 102 formed in a part of at least the uppermost layer in the multilayer wiring structure, an element structure (210, 200) formed on the multilayer wiring structure including the cavity, and at least one stress-relaxing layer 10 for relaxing the stress induced in the first principal surface side of the substrate, formed on a second principal surface opposite to the first principal surface of the substrate.
Inventors:
MIYASHITA KAZUYUKI
Application Number:
JP2010178383A
Publication Date:
February 23, 2012
Filing Date:
August 09, 2010
Export Citation:
Assignee:
SEIKO EPSON CORP
International Classes:
G01J1/02; H01L37/02
Attorney, Agent or Firm:
Masahiko Ueyanagi
Osamu Suzawa
Kazuhiko Miyasaka
Osamu Suzawa
Kazuhiko Miyasaka