Title:
MULTILAYER SUBSTRATE FOR SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP3635219
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a multilayer substrate for a semiconductor device on which a semiconductor element mount surface can be flatly and thinly formed as much as possible.
SOLUTION: In this semiconductor device multilayer substrate 10 on which one surface side, where a conductive wiring 12 is formed through an insulating layer 14, is used as the semiconductor element mounting surface where the semiconductor element pad 20a, to be connected to the electrode terminal 18 of a semiconductor element 16 to be mounted, and the other surface side of the multilayer substrate is used as the external connection terminal mounting surface where an external connection terminal pad 24 is formed; a via 28 where the conductive wiring 12 formed on both surfaces of the insulating layer and/or the pad 20 are electrically connected is formed penetrating the insulating layer 14, and the via 28 is perforated on the external connection terminal mounting surface side of the insulating layer 14. The aperture area where bottom face is formed on the inside surface on the external connection terminal mounting surface side of the conductive wiring 12, formed on the semiconductor element mounting surface side, is formed on a conical-shaped recessed part 30 which is larger than the area of bottom face.
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Inventors:
Akio Rokukawa
Masayuki Sasaki
Yuichi Matsuda
Masayuki Sasaki
Yuichi Matsuda
Application Number:
JP37098499A
Publication Date:
April 06, 2005
Filing Date:
December 27, 1999
Export Citation:
Assignee:
Shinko Electric Industry Co., Ltd.
International Classes:
H01L23/12; H01L23/498; H05K1/11; H05K3/46; H05K3/00; H05K3/04; H05K3/10; H05K3/20; H05K3/38; (IPC1-7): H01L23/12; H05K3/46
Domestic Patent References:
| JP11251476A | ||||
| JP11176870A | ||||
| JP9148699A | ||||
| JP6236940A |
Attorney, Agent or Firm:
Takao Watanuki
Horimai Kazuharu
Horimai Kazuharu