Title:
MULTILAYER WIRING BOARD AND ITS MANUFACTURE
Document Type and Number:
Japanese Patent JP3827447
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide the manufacturing method of an inexpensive multilayer wiring board which is capable of the formation of a wiring layer in high density and besides does not require a polishing process, etc., by forming the wiring layer comprising a low-resistance conductor by simultaneous baking, and preventing the deterioration of the insulation between wiring layers by the diffusion of copper.
SOLUTION: An insulating substrate 1, where a plurality of insulating layers 1a, 1b, and 1c comprising ceramic oxides such as Al2O3 are laminated, and, within the insulating substrate 1, an inner wiring layer 2a comprising the conductor of at least copper single substance or composite material which contains copper, tungsten and/or molybdenum and in which the volume ratio of Cu/(Cu+ W+Mo) is 0.3 or over, for its main components are arranged, and they are baked at the same time within an oxidating atmosphere where the dew point including hydrogen is -20°C or under. Hereby, a substrate excellent in smoothness where the diffusion distance of copper into ceramics around the inner wiring layer 2a is made 20 μm or under and also the average surface roughness (Ra) is 1 μm or under can be obtained.
Inventors:
Masanobu Ishida
Shigeki Yamada
Shigeki Yamada
Application Number:
JP18206598A
Publication Date:
September 27, 2006
Filing Date:
June 29, 1998
Export Citation:
Assignee:
Kyocera Corporation
International Classes:
H05K3/46; (IPC1-7): H05K3/46
Domestic Patent References:
| JP715101A | ||||
| JP6112650A | ||||
| JP4280657A | ||||
| JP2263782A |