Title:
MULTILAYERED WIRING BOARD
Document Type and Number:
Japanese Patent JP3176258
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a multilayered wiring board which effectively prevents generation of disconnection of wiring conductor or through hole conductor is effectively prevented and can ensure electrical connection of each electronic component mounted on an insulating substratum.
SOLUTION: In the title multilayered wiring board, a plurality of wiring conductors 2 are arranged as multilayered structure in an insulating substratum 1 composed of ceramic sintered body, and each of the wiring conductor 2 is connected via through hole conductors 3. When the length of the wiring conductor 2 is L1, the sectional area is S2, the resistivity is σ1, the length of the through hole conductor 3 is L2, the sectional area is S2, and the resistivity of the through hole is σ2, the relation σ1.L1/S1≥σ2.L2/S2 is satisfied.
Inventors:
Kenichi Aihara
Takashi Okunozono
Takashi Okunozono
Application Number:
JP17180595A
Publication Date:
June 11, 2001
Filing Date:
July 07, 1995
Export Citation:
Assignee:
Kyocera Corporation
International Classes:
H05K3/46; (IPC1-7): H05K3/46
Domestic Patent References:
| JP5982794A | ||||
| JP2148889A |