PURPOSE: To eliminate the influence of back-gate effect on an FET for intermediate output without increasing the number of circuit elements greatly and to attain the high integration of a circuit by coupling a capacity element additionally to the FET.

CONSTITUTION: When output control signals I1 ∼ I4 are at the lowest voltage V4, an FET 5 is on and FETs 7, 9 and 10 are off, so that the highest potential V1 is outputted from an output terminal OUT. When the signals I3 and I4 are at a potential V4 and the signals I1 and I2 are at a potential V1, FETs 5, 9 and 10 are off and FETs 7 and 6 are on to supply an intermediate potential V2 to the substrate of the FET 7, so that the terminal OUT is held at a potential V2. Then when the signals I2 and I4 are at the potential V4 and the signals I1 and I3 are at the voltage I1, the FETs 5, 7 and 10 are off and the FETs 9 and 8 on to supply an intermediate potential V3 to the substrate of the FET 9, so that V3 appears at the terminal OUT. When the signals I2 and I3 are at the potential V4 and the signals I1 and I4 are at the potential V1, the FETs 5, 7 and 9 are off and the FET 10 is on, so that the V4 is outputted at the terminal OUT.