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Title:
MULTILEVEL ROM
Document Type and Number:
Japanese Patent JPS56137593
Kind Code:
A
Abstract:

PURPOSE: To increase the storage capacity of mask ROM, by inputting the data of 2-bit or more, to one transistor forming the memory cell array.

CONSTITUTION: When the data in n-bit is inputted to one cell, it is required for the threshold voltage to be 2n level, and this can be made by using n-sheet of masks. Thus, when data in 2-bit is inputted to one cell, 4-level of threshold voltage is required and it can be done with two masks A, B. The memory cell array 4 is formed by using the transistor programmed to the threshold voltage with two masks, and the output of the array 4 selected with the address recorder 19 is given to the A/D converter 23 via the multiplexer 23. The converter 23 is output after being converted into 4 digital values. Thus, the storage capacity of mask ROM can be increased.


Inventors:
MIKAMI MASAHIRO
Application Number:
JP3946780A
Publication Date:
October 27, 1981
Filing Date:
March 27, 1980
Export Citation:
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Assignee:
SUWA SEIKOSHA KK
International Classes:
G11C16/04; G11C17/00; (IPC1-7): G11C7/00



 
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