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Patent Searching and Data


Title:
MULTIPLE ARRANGEMENT MULTILAYER WIRING BOARD
Document Type and Number:
Japanese Patent JP2004055841
Kind Code:
A
Abstract:

To overcome a problem that it is impossible to mount electronic elements correctly and surely on each wiring board region since a crack generated at the end of a dividing groove in a motherboard extends to the periphery of the motherboard, and then extends to the wiring board regions also.

In a multiple arrangement multilayer wiring board, wiring board regions divided by each dividing groove 2 whose ends are spaced apart from the periphery of the motherboard 1 are arranged on the upper surface of the motherboard 1 which is formed by laminating a plurality of ceramic insulation layers. Further, in the board, a frame-like metallized layer 4 which surrounds the wiring board regions is arranged in between ceramic insulating layers positioned just under the tip of the dividing groove 2 and between each end of the dividing groove 2 and the periphery of the motherboard 1. Since extension of the crack started from the end of the dividing groove 2 to the periphery of the motherboard 1 can be effectively blocked by the metallized layer 4, extension of the crack to the wiring board regions is terminated, thereby enabling electronic elements to be mounted on each wiring board region correctly and surely.


Inventors:
OUCHI TAKUYA
HIROMORI MASATAKA
Application Number:
JP2002211586A
Publication Date:
February 19, 2004
Filing Date:
July 19, 2002
Export Citation:
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Assignee:
KYOCERA CORP
International Classes:
H05K1/02; H01L23/13; H05K3/46; (IPC1-7): H05K3/46; H01L23/13; H05K1/02