Title:
MULTIPLE FREQUENCY DIGITAL PHASE-LOCKED LOOP
Document Type and Number:
Japanese Patent JP2541398
Kind Code:
B2
Abstract:
PURPOSE: To deviate an operation frequency by providing a phase comparing means, a clocking means, a programmable dividing means, a digital means that generates a clock signal, an adjusting means which adds or subtracts and a dividing means.
CONSTITUTION: A multiple frequency digital phase-locked loop is equipped with frequency dividers 26 and 28 between a clock input 14 and an AND gate 30, and the frequency divider 28 receives programmable inputs Y and Z which carry out various dividing ratios. Control signals Y, Z and X co-operate with a bandwidth control circuit 20 and change loop correction bandwidth through a loop operation frequency. The signal X co-operates with a phase and frequency adjusting circuit network 12 controls the command of frequency correction by a digital phase-locked loop. An input to a phase comparator 18 is connected to an OR gate 24 and further connected to a clock detector 22. In this way, the circuit 20 changes loop bandwidth by changing the number of digital pulses which are added or subtracted from a composite clock, and performs loop phase adjustment.
Inventors:
REUAIN SUTEIIBUN ENU
Application Number:
JP18801791A
Publication Date:
October 09, 1996
Filing Date:
July 02, 1991
Export Citation:
Assignee:
MOTOROLA INC
International Classes:
H03D13/00; H03K5/00; H03K5/26; H03K5/13; H03K5/22; H03K23/66; H03L7/00; H03L7/06; H03L7/085; H03L7/095; H03L7/099; H04L7/033; (IPC1-7): H03L7/06
Domestic Patent References:
| JP738427A | ||||
| JP738428A |
Attorney, Agent or Firm:
Shinsuke Onuki (1 person outside)