PURPOSE: To shorten a waiting time for an access to a main memory device by regulating plural central processing units (CPUs) to fix timing, with which the request of the access to the main memory device is executed to a system controller, and limiting the number of the CPUs which can execute simultaneous requests.

CONSTITUTION: A timing regulating means A is provided to regulate the plural CPUs 1a-1d so that the timing to execute the request of the access to a main memory device 4 can be fixed to a system controller 3 and a request priority order deciding means B is provided to limit the number of the CPUs 1a-1d which can execute the simultaneous requests. A priority order deciding circuit 5a accepts one request at a maximum and a timing generator 6 generates a requestable signal to regulate the respective CPUs 1a-1d so that the timing to execute the request can be fixed. Thus, the number of the CPUs 1a-1d to be simultaneously requestable is limited and the waiting time for the access to the main storage device 4 can be shortened.