PURPOSE: To provide the multiplexer circuit of a low power consumption for suppressing the degradation in waveform of a signal and for reducing the number of multiplexers to require the sharpness of a control signal, which is suitable to the high-speed operation.

CONSTITUTION: A multiplexer circuit 1 is provided with nine multiplexers 11 to 19 and a control circuit 20. Each of multiplexers 11 to 19 has two input terminals A and B, one output terminal Z, and a control signal terminal S. Multiplexers 11 to 19 are connected like a two-divided tree having height 3 by eight connection lines 41 to 48 connecting input terminals A or B and output terminals Z. The control circuit 20 outputs control signals c1 to c4 to control signal terminals S of multiplexers 11 to 19 to control multiplexers 11 to 19 so that a parallel signal ID consisting of ten signals d0 to d9 is converted to a serial signal OD consisting on ten signals d0 to d9.