Title:
MULTIPLEXER CIRCUIT
Document Type and Number:
Japanese Patent JP2004173168
Kind Code:
A
Abstract:
To overcome a problem such that in a multiplexer circuit, it becomes difficult to sufficiently secure a band for reducing the voltage and for making a fast operation of the small signal complitude.
This multiplexer circuit which synchronizes parallel data PD0 to PD3 with internal clocks 0 to 3 and converts the parallel data into serial data SD is provided with a logic circuit 2 for the internal locks and the parallel data, and a load circuit 1 and a plurality of switch elements 30 to 33 connected in series between a first power source line Vdd and a second power source line Vss. Each of the switch elements is configured so as to be controlled by an output of the logic circuit.
Inventors:
MASAKI SHUNICHIRO
Application Number:
JP2002339307A
Publication Date:
June 17, 2004
Filing Date:
November 22, 2002
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H03K17/00; H03K17/693; H03M9/00; (IPC1-7): H03K17/693; H03K17/00
Attorney, Agent or Firm:
Takashi Ishida
Jun Tsuruta
Shigeru Tsuchiya
Masaya Nishiyama
Higuchi Souji
Jun Tsuruta
Shigeru Tsuchiya
Masaya Nishiyama
Higuchi Souji
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