To operate a multiplexer normally by providing a variable delay circuit connecting to a control circuit to a data input side of a retiming use D-FF at a final output stage in the multiplexer so as to adjust each timing.

A 1st stage of a multiplexer 100 is made up of 2:1 multiplexer blocks 1, 2 receiving a 1/4 CLK as a clock input and converting parallel data into serial data. A 2nd stage of the multiplexer is made up of a 2:1 multiplexer block 3 receiving a 1/2 CLK as a clock input, and a final output stage is made up of a retiming use D-FF 4 using a high speed clock CLK as a clock input. A variable delay circuit 10 connecting to a control circuit 30 is provided to a data input side of the D-FF 4. Thus, each timing for data input, clock input, and frequency division clock input is adjusted and even when a fluctuation in delay of circuit components due to fluctuation in a device parameter or a temperature takes place, the normal operation of the multiplexer is ensured.