PURPOSE: To reduce the hardware used for the multiplication circuit, by shifting and supplying the least significant bit of the operation resulting register to the most significant bit of the multiplication register every unit processing.

CONSTITUTION: When the multiplication processing is started, the multiplier and multiplicand are respectively set to the multiplier register 3 and the multiplicand register 2 and the content of the operation resulting register 1 is cleared. Next, the content of the register 1 is shifted right by one bit with the shift 4 and the result of shift is input to the logic operation unit 5. Further, the check whether or not the least significant bit of the register 2 is 1 is made and if the result is 1, the content of the register 1 input to the input port and the multiplicand are added at the unit 5 and the result of addition is delivered to the register 1. Further, if the least significant bit of the register 3 is 0, the content of the register 1 input is set to the register 1 via the unit 5 and simultaneously the register 3 is shifted right by one bit and the least significant bit of the register 1 is shifted to the most significant bit of the register 3.