To provide a multiplier having a complete tree of 4-2 compressors structured by signed multiplication.
In a signed multiplier having partial products structured by secondary booth decoding, a booth selector part 101 is provided with a partial- product correcting circuit 103 for correcting the partial products by using a booth decoding output as an input. This reduces the number of partial products and makes it possible to conduct partial product addition of a two-piece tree structure by the 4-2 compressors 104. Carry propagation addition 105 is made to the result of the partial product addition to provide the result of multiplication. Since a complete two-piece tree of 4-2 compressors can be structured especially with 8 bits, 16 bits, and 32 bits, speeding up can be made by a difference in delay time between a two-stage series 3-2 adder and the 4-2 compressors as compared with a conventional structure using a 3-2 adder.
| JPH079649 | [Title of Invention] Microcomputer device |
| JP3612950 | Arithmetic logic unit and its method |
| JPH08179932 | ARITHMETIC UNIT |
ARAKAWA FUMIO
NAGATA KENJI
