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Patent Searching and Data


Title:
MULTIPLIER
Document Type and Number:
Japanese Patent JPH04142619
Kind Code:
A
Abstract:

PURPOSE: To make it possible to use a multi-bit data multiplier as plural small number bit data multipliers to be operated at a time by providing the present multiplier with plural decoders installed for a booth of predetermined bits, a carry control circuit for predetermined bits of a 3X generating circuit, and a selector installed as part of a sign bit adding circuit.

CONSTITUTION: The present multiplier is provided with plural decoders Ca5 and Cb5 installed for a booth of predetermined bits, a carry control circuit for predetermined bits of 3X generating circuit, and a selector installed in a part of a sign bit adding circuit. That is, two booth decoders Ca5 and Cb5 are installed for Ya data and Yb data. With this, one multi-bit data multiplier can be used as plural small bit data multipliers to operate small bit data items at a time.


Inventors:
HIRASAWA MASAO
Application Number:
JP26677990A
Publication Date:
May 15, 1992
Filing Date:
October 04, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F7/533; G06F7/52; G06F7/53; (IPC1-7): G06F7/52
Attorney, Agent or Firm:
Uchihara Shin