PURPOSE: To accelerate the arithmetic speed of a multiplier for successively adding partial products without increasing the number of adders.

CONSTITUTION: By using a partial product circuit 105 for inputting a value shifting a multiplicand to a high order by one bit when the two bits of a multiplier are '10' for outputting the multiplicand when the two bits of the multiplier are '01' or '11' and for outputting '0' when the two bits of the multiplier are '00', a variable shifter 109 for selectably shifting the shift amount of one bit or two bits, sum of products register 107 for selecting the shift amount of one bit or two bits and AND circuit 110 for judging whether the two bits of the multiplier are '11' or not, a partial product is processed for the unit of one bit when the two bits of the multiplier are '11', and the partial product is processed for the unit of two bits when the two bits of the multiplier are '00', '10' or '01'.