PURPOSE: To obtain a multiplier circuit which can calculate at a high speed by using the output a partial addition means as the shift-in data which shifts a partial product with the multiplication of low-order (n) bits of a multiplicand.

CONSTITUTION: In the multiplication of low-order (n) bits of a multiplicand, the carry data, the product of an adder 16 performs addition among a multiplicand of the (n+1)-th bit obtained by a selection circuit 15 and a multiplier of the 2nd bit, and the least significant bit of the adder output, i.e., the data of the (n+1)- th bit obtained from an operation where the high-order (n) bits held by a register 22, a multiplicand and a bit of a multiplier. The result of said addition is used as the shift-in data of a shift circuit 7. For multiplication of the multiplicand of upper (n) bits, the carry data of the multiplication of the lower (n) bits stored in a register 23 is used as a subject of addition. The above-mentioned action is repeated until the n-th bit of the multiplier. Thus the result of multiplication of 3n bits can be obtained from registers 3, 13 and 4.