PURPOSE: To increase the multiplying speed of a multiplier by selecting the output of a 1st or 2nd adder train in response to '1' and '0' of the final stage carry output of a 1st adder train.

CONSTITUTION: An adder train which transmits the carry of the final stage to the higher digits is divided into a 1st half adder train 11 and a 2nd latter adder train 12. These trains 11 and 12 perform additions in parallel and simultaneously. A 3rd adder train 13 is added in parallel to the train 12. A carry '1' is supplied to the train 12 with a carry '0' supplied to the train 13 respectively. Then the output of the train 12 or 13 is selected in response to '1' or '0' of the final output of the train 11. The trains 11W13 have carry look-ahead circuits 4 in parallel with each other. The train 12 has higher 6W11 bits of the final stage adder train in the case of a (8×8)-bit multiplier. Thus the multiplying speed is increased.