Title:
MULTIPLYING CIRCUIT FOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3908065
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a multiplying circuit for an integrated circuit whose arithmetic speed is improved.
SOLUTION: This multiplying circuit for an integrated circuit is configured by arranging and connecting a plurality of one bit adders F1 to F20 in a multiple-stage and multiple-digit array so that the multiplier (a) and multiplicand (b) of a plurality of digits can be sequentially inputted to different adders F1 to F20 in the order of digits wherein the individual address F1 to F20 output addition results s1 to s20 and carry signals c5 to c24. As for the input side connection of the respective address F1 to F20, the delay time of the addition result inputs from the pre-stage address are compared with the delay time of the carry signal inputs from the pre-stage and full digit address, and when the delay time of the addition result inputs is larger than the delay time of the carry signal inputs, the addition result inputs and the carry signal inputs from the pre-stage adders are exchanged and connected.
Inventors:
Tsutomu Shimotoyo
Application Number:
JP2002080001A
Publication Date:
April 25, 2007
Filing Date:
March 22, 2002
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
G06F7/53; G06F7/52; (IPC1-7): G06F7/52
Domestic Patent References:
| JP5265716A | ||||
| JP60045842A |
Attorney, Agent or Firm:
Minoru Maeda
Youichi Yamagata
Youichi Yamagata
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