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Title:
MULTIPLYING CIRCUIT
Document Type and Number:
Japanese Patent JPH08171601
Kind Code:
A
Abstract:

PURPOSE: To improve the resolution of multiplication while suppressing the increase of the total number of unit capacitances by providing plural stages of capacity coupling for setting a multiplier, and connecting the preceding stage of capacity coupling to one or plural capacitances on the following stage of capacity coupling.

CONSTITUTION: This multiplying circuit is provided with two stages of inverted amplifiers INV1 and INV2, and feedback capacitances cf1 and cf2 for feeding their outputs back to the inputs are connected to the respective inverted amplifiers. A capacity coupler CP1 is connected to the input terminal of INV1, and an analog voltage Vin is respectively parallelly connected through switching means SW4-SW7 to respective capacitances C4-C7 of the CP1. A coupling capacitance Co1 is connected to the input terminal of INV2, and the output of INV1 is connected through the Co1 to the INV2. Besides, a capacity coupler CP2 is composed of capacitances C3-C0. Therefore, since this circuit is constituted to execute the plural stages of multiplication, the increase of the total number of unit capacitances can be suppressed.


Inventors:
KOTOBUKI KOKURIYOU
YAMAMOTO MAKOTO
TAKATORI SUNAO
Application Number:
JP22471495A
Publication Date:
July 02, 1996
Filing Date:
August 09, 1995
Export Citation:
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Assignee:
SHARP KK
YOZAN KK
International Classes:
G06J1/00; G06G7/16; (IPC1-7): G06G7/16
Attorney, Agent or Firm:
Yamamoto Makoto



 
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