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Title:
MULTIPLYING CIRCUIT
Document Type and Number:
Japanese Patent JPS63308687
Kind Code:
A
Abstract:

PURPOSE: To stabilize an operation by a low voltage, by constituting a multiplying amplifier of plural differential amplifiers, and also, connecting plural current mirror circuits.

CONSTITUTION: A base voltage V1 of transistors TR Q1, Q2 and a base voltage V2 of TRs Q3WQ6, and a collector voltage V3, which are required for an operation of the circuit become V1≥0.8V, V2≥1.1V, and V3≥0.7V, and when the base voltage V2 of the TRs Q3WQ6 is set to a power supply voltage, and VR1 and VR2 are set to ≤0.4V as VR1=VR2≤V3-V2=0.4V, this circuit is operated. In this case, a bias of T1 is connected through a resistance from Tcc, and a signal is applied to T1 by capacitor coupling. In such a way, the circuit is operated stably by Vcc=1.1V, and a subtractive voltage characteristic is improved.


Inventors:
HIRASAWA MASAHIRO
YOKOYAMA RYOICHI
Application Number:
JP14562687A
Publication Date:
December 16, 1988
Filing Date:
June 10, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06G7/163; (IPC1-7): G06G7/163
Domestic Patent References:
JPS57139871A1982-08-30
JPS6090407A1985-05-21
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)