PURPOSE: To enable sharing an address decoder with plural ports by operating the decoder from outside as a multiport memory synchronizing with CLK.

CONSTITUTION: A clock multiplying device 103 multiplies an out side clock 103 and generates a selection signal SEL, a port clocks ACLK and BCLK. During a period of time when the port A is selected by the selection signal SEL, the address decoder 102 decodes an address inputted from the port A and corresponding data are read out from a memory array 104. Similarly, during a period when the port B is selected, the address decoder 102 decodes an address inputted from the port B and corresponding data are read out from the memory array 104. The data A outputted through a data selector 106 are held by the port clock ACLK and BCLK.