PURPOSE: To efficiently re-distribute a data array among processors and to optimize the use of a local memory inside the respective processors by providing independently programmable read detector and write detector in the respective processors.

CONSTITUTION: The respective processor 32 are provided with means connected to the processor 32 for detecting the identification information of data required by the processor and reading the data corresponding to label information detected from a communication bus line 36, that are a link 34 and an MD decoder & memory address generator 52. Also, the respective processor 32 are provided with the means connected to the communication bus line 36 for detecting the label information of the data stored at present by the processor and writing the data corresponding to the detected label information to the communication bus line, that are the link 34 and the MD decoder and memory address generator 52. Thus, the data array is efficiently re-distributed among the processors and the use of the local memory inside the respective processors is optimized.