Title:
MULTIPROCESSOR INTERRUPTION CONTROL SYSTEM
Document Type and Number:
Japanese Patent JP2848297
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To distribute an interruption load equally to respective processors fast by making an I/O device control means control the transmission of an interruption request to a processor having the lightest interruption load according to the contents of a transaction.
SOLUTION: This system is provided with processor control circuits 200-1 to 200-4 corresponding to processors 100-1 to 100-4 and I/O device control circuits 300-1 and 300-2 which accept interruptions from plural I/O devices 500-1 to 500-6 through interruption lines 600-1 and 600-2. Processor control circuits 200-1 to 200-4 inform the I/O device control circuits 300-1 and 300-2 of the interruption loads of the corresponding processors and the I/O device control circuits 300-1 and 300-2 controls the transmission of the interruption request to the processor having the lightest interruption load according to the contents of the transaction.
Inventors:
ABE KUNIKI
Application Number:
JP31825895A
Publication Date:
January 20, 1999
Filing Date:
December 06, 1995
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G06F15/16; G06F9/46; G06F9/50; G06F13/24; G06F15/163; G06F15/177; (IPC1-7): G06F15/163; G06F9/46; G06F13/24
Domestic Patent References:
| JP5324570A | ||||
| JP6180688A | ||||
| JP5204824A | ||||
| JP7244649A | ||||
| JP59136862A | ||||
| JP394360A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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